There is one "pure" global scratch register which compiler doesn't use and you can not use for computation, for Blackfin architecture. That is USP. Yes. If your code always in the supervisor mode, nobody need to keep USP. I hesitate to use…

VisualDSP++ 3.5 can generate codes which avoid anomalies of each version of silicon. Usually anomaly avoidance code degrades performance, you should use this feature carefuly. Revesion can be specified as following : -si-revision 0.2 My EZ…

The Anomaly #55 of ADSP-BF533 Rev0.2 says : The CDPRIO bit in the EBIU_AMGCTL register selects the priority of core vs. DMA accesses to external memory. This bit is not functional and set to zero. Therefore, core accesses have always prior…

ADSP-BF533 has dedicated DMA for each transmitter of receiver of UART. You can reduce the load of processor by using DMA. When you use the UART DMA, you should be careful to set the ETBEI and ERBFI of UART_IER to 1 for TX DMA and RX DMA, r…

The UART controller of ADSP-BF533 is 16450 compatible. If you used to program PC since ‘80th or know well about IPs, you may realize that this doesn’t have FIFO buffer. No PC uses this these days. The buffered type 16550A was developed to …

If you see the data sheet of 750MHz BF533, You will find it consume 16mA even you stop the core clock, at 0.8V VDD. That is what you have to pay for high speed process. Any way, you should know this if you think about long stand by applica…

Some of the MMR changes its state if you read it. Most of MMR is not like this. But some legacy devices which requires compatibility does. The UART is the typical legacy devices. Once you read the UART_IIR or UART_RBR, the state of UART is…

See the above picture. This is a capture of VisualDSP++ during the debugging of TOPPERS/JSP interrupt handler, entry part. I got following message when I reach here by step execution. Dag0 Prot Violation !32 bit access You can see DAG0 cau…