Anomaly #55
The Anomaly #55 of ADSP-BF533 Rev0.2 says :
The CDPRIO bit in the EBIU_AMGCTL register selects the priority of core vs. DMA accesses to external memory. This bit is not functional and set to zero. Therefore, core accesses have always priority over DMA accesses, when the two requests occur simultaneously.
This simple description doesn’t explain there is non-intuitive pitfall.
It seems to be not so strange that core access has higher priority than DMA does, if you think about DMA is the background transfer mechanism. Probably, this setting itself is very reasonable.
The problem is in the FIFO design. DMA set it’s priority as “urgent” when TX FIFO becomes empty or RX FIFO becomes full. Under the urgent priority, DMA can override any other bus-master to access external RAM. This sounds OK. But you cannot stop on-going burst access even you have urgent priority. This brings certain latency to give you to access the external SRAM. This latency is no problem for SSI, but problematic for PPI video transfer. Usually, such the “urgent” mode have to be triggered several depth before FIFO get full or empty.
Probably, if you use both
to external SDRAM, you will get broken video.
There is no work around. The large application usually needs instruction cache. Anomaly says next revision of silicon will fix this. If you need schedule, you should contact ADI person.
